The asynchronous operation CMOS TTL (complementary metal oxide semiconductor transistor-transistor logic) input buffer has two major obstacles that have been taunting IC (integrated circuit) designers for years. The first obstacle is the variation of input trip point (the point beyond which an output responds to a change in an input) across power supply, process and temperature. The second obstacle is the high power dissipation of the buffer's first stage inverter, which results from the small voltage swing of the TTL input level. Furthermore, for compatibility to standby power requirements of the existing products, a CMOS input buffer often must be gated by an enabling signal for switching to and from the standby mode (a mode of wherein the buffer is not operational and thus shut off to conserve power). A typical prior art CMOS input buffer is shown in FIG. 1 wherein an enable signal and an input signal are inputs to nor gate 3 which feeds first stage inverter 5 which in turn feeds second stage inverter 7. These problems require compromises to be made between speed, power, yield and reliability, and thus tend to degrade the overall performance of the device. FIG. 2 shows a plot of DC trip point vs. buffer supply voltage Vcc for the prior art CMOS input buffer shown in FIG. 1. TTL VIH represents a TTL high level while TTL VIL represents a TTL low level. The transistor sizes of the buffer's first stage inverter are chosen such that the DC trip point is centered at a midpoint of the TTL input level (1.4 volts). However, as shown in FIG. 2, as process, power supply and temperature fluctuate, the DC trip point deviates away from the midpoint and reduces the input signal margins. Additionally, a significant current is flowing through nor gate 3 of the CMOS input buffer of FIG. 1 when its input is at the TTL VIH level of 2.0 volts, resulting in much undesired power dissipation. FIG. 3 shows a plot of this current vs. input voltage VIN into the buffer.